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PRELIMINARY PRODUCT SPECIFICATION
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Z86319
PS/2 MOUSE CONTROLLER
FEATURES
Device Z86319 ROM (KB) 2 RAM* (Bytes) 125 I/O Lines 13 Voltage Range 4.5V to 5.5V
s
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P24-P27 Can Be Configured with a Voltage Divider During Input Mode On-Chip Oscillator (Tolerance = 10%) Fast Instruction Pointer: 1.5 s @ 4 MHz ESD Protection Circuitry Hardwired Watch-Dog Timer (WDT) Excellent System Level EMI/EFT/ESD
s s
Note: *General-Purpose (144K Total RAM) s s
0C to + 40C Operating Temperature Range Low-Power Consumption: 25 mW (Typical)
s s s
GENERAL DESCRIPTION
The Z86319 is a member of the Z8 family of CMOS microcontrollers architecture to be used in mouse applications. These devices offer on-board pull-up and pull-down resistors, a trip-point buffer to accommodate opto-transistor outputs, and high drive ports capable of up to 10 mA current sinking per pin (3 pins maximum). A permanently enabled Watch-Dog Timer ensures operational reliability across a broad range of mouse application environments. The precision RC oscillator filters out highfrequency noise from the oscillator input pin. When configured as inputs, P24-P27 have built in voltage dividers (25K pull-up /7.5K pull-down). The input levels are designed for connection to the emitters of the opto-transistors and switch at a voltage level of 0.4 VDD. For applications requiring powerful I/O capabilities, the Z86319 provides dedicated input and output lines that are grouped into three ports. There are two basic address spaces available to support this configuration: Program Memory, and 125 bytes of general-purpose registers. The Z86319 device provides two on-chip 8-bit programmable counter/timers with a large number of user-selectable modes. Each counter/timer is driven by its own 6-bit programmable prescaler. The Z86319 counter/timers off-load system real-time tasks such as counting/timing and input/output data communications for increased system efficiency.
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GENERAL DESCRIPTION (Continued)
Input
VDD
GND
AGND
RCIN
Port 3
Machine Timing & Inst. Control
ALU Counter/ Timers (2) Prg. Memory 2048 x 8-Bit
FLAG
Interrupt Control
Register Pointer Register File 144 x 8-Bit
Program Counter
Port 2
Port 0
WDT
I/O (Bit Programmable)
I/O
Figure 1. Z86319 Functional Block Diagram
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PIN DESCRIPTIONS
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P24 P25 P26 P27 VDD RCIN AGND P31 GND 1 18
18 - Pin DIP/SOIC
9
10
P23 P22 P21 P20 GND P02 P01 P00 P33
Figure 2. 18-Pin DIP/SOIC Pin Configuration Table 1. 18-Pin DIP/SOIC Pin Identification Pin # 1-4 5 6 7 8 9 10 11-13 14 15-18 Symbol P24-P27 VDD RCIN AGND P31 GND P33 P00-P02 GND P20-P23 Function Port 2, Pins 4,5,6,7 Power Supply RC Oscillator Analog Ground Port 3, Pin 1 Ground Port 3, Pin 3, Port 0, Pins 0,1,2 Ground Port 2, Pins 0,1,2,3 Direction In/Output Power Input Ground Input Input Input In/Output Ground In/Output
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PIN FUNCTIONS
RCIN. A precision 1% resistor is connected to RCIN, generating oscillation with an internal capacitor. Resistor values and corresponding typical frequencies are shown in Table 2 and graph chart (Figure 3). Table 2. Resistor Values and Corresponding Typical Frequencies External Resistor 14.0K 15.0K 16.0K 17.0K 18.0K 19.0K 20.0K 21.0K 22.0K 23.0K Average Frequency 5.01 MHz 4.70 MHz 4.43 MHz 4.19 MHz 3.97 MHz 3.78 MHz 3.60 MHz 3.44 MHz 3.30 MHz 3.16 MHz
6
5
FREQUENCY (MHz)
4
3
2
1
0 14 15 16 17 18 19 20 21 22 23 RESISTOR VALUE (K OHMS)
Figure 3. Z86319 RC Frequency in Function of the External Resistance (typical numbers)
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STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to Ground. Positive current flows into the referenced pin (Figure 4).
From Output Under Test
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I 150 pF
Figure 4. Test Load Diagram
ABSOLUTE MAXIMUM RATINGS
Sym VDD TSTG TA Parameter Supply Voltage* Storage Temp Oper Ambient Temp Min -0.3 -65 0 Max +7 +150 40 Units V C C Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This rating is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Notes: *Voltages on all pins with respect to Ground.
CAPACITANCE TA = GND = 0V, f = 1.0 MHz, unmeasured pins returned to Ground.
Parameter Input Capacitance Output Capacitance I/O Capacitance Min 0 0 0 Max 10 pF 20 pF 25 pF
VCC SPECIFICATION
VCC = 4.5V to 5.5V Using the precision RC oscillator feature, f = 4.0 MHz 10% under the following conditions:
s s s
VCC = 5.0V 10% Temp 0 to 40C Application board capacitance: - 2.0 pF max. - 0.5 pF min.
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DC ELECTRICAL CHARACTERISTICS 4.5V VDD 5.5V
TA = 0C to +40C Sym VIH VIL VIL VOH VOL1 VOL2 VLV VTP IIL IOL IDD IDD1 IPU IPD IPU Parameter Rising Input Schmitt-Triggered Falling Input Schmitt-Triggered Input Low Voltage CMOS Input Output High Voltage Output Low Voltage Output Low Voltage VCC Low Voltage Protection Trip Point Voltage (P24-P27) Input Leakage Output Leakage Supply Current Standby Current Pull-Up Current (100K) P00-02, P31, P33 Pull-Down Current (100K) P00-02, P31, P33 Pull-Up Current (10K) P20, P22 -370 -670 +20 +85 -20 -95 2.25 1.9 1.5 -1.0 -1.0 Min 2.3 1.3 Max 3.2 2.2 Units V V V VDD - 0.4 0.4 0.8 2.95 2.5 2.1 1.0 1.0 4.5 2.2 V V V V V V A A mA mA A A A A A A IOH = -2.0 mA; VDD=4.5V IOL = +4.0 mA; VDD=5.5V IOL = 10.0 mA, 3 Pin Max; VDD=5.5V @ 4 MHz Max, Note 2 P24-P27; VDD=5.5V VDD=4.5V VIN = 0V, or VCC Note 4 VIN = 0V, or VCC Note 4 @ 4 MHz, Note 3; VDD=5.5V @ 4 MHz, Note 3; VDD=5.5V VIH @ 1V VIH @ 1V VIL @ 3V VIL @ 4V VIL = 0V VIL = 0V Conditions Note 1 Note 1
Notes: 1. The min. and max. values of the Schmitt-Trigger input voltages track each other over temperature, VDD, and process variations. 2. The device is functional from VDD down to VLV voltage. The minimum operational VDD is determined by the value of the VLV voltage at ambient temperature. The VLV voltage increases as the temperature decreases. 3. All input pins are tied to GND and all output pins are floating.
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AC ELECTRICAL CHARACTERISTICS Timing Diagrams
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1 1
T
IN
2 4 3
IRQ
N
5 6
Figure 5. Electrical Timing Diagram
TA = 0C to +40C No 1 2 3 4 5 6 Symbol TrTin, TtTin TwTinL TwTinH TpTin TwIL TwIH Twdt TPOR TpC Parameter Timer Input Rise and Fall Time Timer Input Low Width Timer Input High Width Timer Input Period Int. Request Input Low Time Int. Request Input High Time Watch-Dog Timer Time Out Power-On Reset Time RC Oscillator Clock Period VDD 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V Min 70 2.5TpC 4TpC 70 2.5TpC 10 2 220 Max 100 Units ns ns Notes 1 1 1 1 1,2 1,2
ns ms ms ns
10 5000
Notes: 1. Timing Reference uses 0.9 VDD for a logic 1 and 0.1 VDD for a logic 0. 2. Interrupt request through Port 3 (P33-P31)
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PIN FUNCTIONS
Port 0 (P02-P00). Port 0 is a 3-bit, I/O programmable, bidirectional, CMOS-compatible I/O port. These three I/O lines can be configured under software control to be input or output (Figure6). When Port 0 is configured as an input port, all lines have the capability to either sink or source (ROM mask selectable) current emulating a 100K pulldown or pull-up resistor. Port 00-02 can be accessed through the P0 register (register address 00). The upper 5 bits of this 8-bit register always reads "11111." Writing to the upper 5 bits has no effect (see Figure 34). The lower 3 bits of the P0 register are read/write. Current versus pin voltage graphs are shown in Figures 7 and 8.
Pull-Up Enable (Mask Option)
OE Pad
Out
In
Pull-Down / Enable (Mask Option)
Figure 6. Port 0 Configuration
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vdrain
Figure 7. Current vs Pin Voltage Values
Figure 8. Current vs Pin Voltage Values
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PIN FUNCTIONS (Continued)
Port 2 (P27-P20). Port 2 is an 8-bit, bit programmable, bidirectional, CMOS-compatible I/O port. These eight I/O lines can be configured under software control to be input or output, independently. Bits programmed as outputs may be globally programmed as either push-pull or opendrain. When configured as inputs, P20 and P22 have 10 kOhm (typical) pull-up resistors (Figure 9). However, P21 and P23 do not have resistors (Figure 10). When configured as inputs, P24-P27 are configured with a voltage divider. The voltage divider consists of an internal 25K pull-up resistor (Figure 11), and a 7.5K pull-down resistor. The input levels on P24-P27 are adjusted for connection to the emitters of the opto-transistors and switch at a voltage level of 0.4 VDD ( 300 mV). For input voltages on P24-P27, refer to Table 3. Table 3. P24-P27 Input Open Circuit Voltage (No off-chip resistance) VDD 4.5V 5.0V 5.5V Min 0.95V 1.05V 1.15V Max 1.15V 1.25V 1.39V
VDD Open-Drain OE
10 Kohm, 20%
Pad
Out
In
Figure 9. Port 2 P20, P22 Configuration
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VDD Open-Drain OE
1
Pad
Out
In
Figure 10. Port 2 P21, P23 Configuration
Resistance Tolerance (0-40C) Min. Pull-Down Pull-Up 5.2K 18K Max. 8.9K 30K
25K
7.5K
Open-Drain
OE
Pad Out
In
0.4 VDD 300 mV Trip Point Buffer
Figure 11. Port 2 P27-P24 Configuration
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PIN FUNCTIONS (Continued)
Port 3 (P33, P31). Port 3 is a 2-bit, CMOS-compatible port with two fixed input lines (P33, P31). These two lines can also be used as the interrupt sources IRQ2 and IRQ1. P31 can also be configured as a timer input. Both lines can be configured through ROM mask selection to sink or source current emulating a 100K pull-up or pull-down resistor (Figure 12). Port 33-31 can be accessed through the P3 register. The upper 4 bits of this 8-bit register always reads "1111." Bit D2 reads 0 and Bit D0 reads 1. Bits D3 and D1 represent P33 and P31 respectively (see Figure 36).
Pull-Up Enable (Mask Option) Pad P31 Data Latch IRQ2, TIN Pull-Down/Enable (Mask Option)
Pull-Up Enable (Mask Option) Data Latch Pad P33 Pull-Down/Enable (Mask Option) IRQ1
Figure 12. Port 3 P33, P31 Configuration
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FUNCTIONAL DESCRIPTION
The Z86319 MCU incorporates the following special features to enhance the Z8 architectural core for use in mice, trackballs, and other consumer applications. Reset. Upon power-up, the Power-On Reset circuit waits for TPOR, plus 18 clock cycles, then starts program execution at address 000CH (Figure 13). The Z86319 control registers' reset values are shown in Table 4.
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RC OSC
POR (Cold Start)
Delay TPOR
18 CLK Reset Filter
Chip Reset
Figure 13. Internal Reset Configuration Table 4. Z86319 Control Registers Reset Values Addr. F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FF Reg. TMR T1 PRE1 T0 PRE0 P2M P3M P01M IPR IRQ IMR FLAGS RP SPL D7 0 U U U U 1 U U U U 0 U U U D6 0 U U U U 1 U U U U U U U U D5 0 U U U U 1 U U U 0 U U U U D4 0 U U U U 1 U 0 U 0 U U U U D3 0 U U U U 1 U U U 0 U U U U D2 0 U U U U 1 U U U 0 U U U U D1 0 U 0 U U 1 1 0 U 0 U U U U D0 0 U 0 U 0 1 0 1 U 0 U U U U Comments
Inputs after reset
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FUNCTIONAL DESCRIPTION (Continued)
Program Memory. The Z86319 can address up to 2 KB of internal program memory (Figure 14). The first 12 bytes of program memory are reserved for the interrupt vectors. These locations contain four 16-bit vectors that correspond to the four available interrupts. Bytes 0-2047 are on-chip mask-programmed ROM. Register File. The Register File consists of three I/O port registers, 125 general-purpose registers, and 14 control and status registers, R0-R3, R4-R127 and R241R255, respectively (Figure 15). The Z86319 instructions can access registers directly or indirectly via an 8-bit address field. This field allows short, 4-bit register addressing using the Register Pointer. In the 4-bit mode, the register file is divided into eight working register groups, each occupying 16 continuous locations. The Register Pointer addresses the starting location of the active working-register group.
2047 Location of First Byte of Instruction Executed After RESET On-Chip ROM 12 11 10 9 8 Interrupt Vector (Lower Byte) 7 6 5 Interrupt Vector (Upper Byte) 4 3 2 1 0 IRQ5 IRQ5 IRQ4 IRQ4
LOCATION R255 R254 R253 R252 R251 R250 Stack Pointer (Bits 7-0) General-Purpose Register Pointer Program Control Flags Interrupt Mask Register Interrupt Request Register Interrupt Priority Register Ports 0-1 Mode Port 3 Mode Port 2 Mode T0 Prescaler Timer/Counter0 T1 Prescaler Timer/Counter1 Timer Mode
IDENTIFIERS SPL GPR RP FLAGS IMR IRQ IPR P01M P3M P2M PRE0 T0 PRE1 T1 TMR
Reserved Reserved IRQ2 IRQ2 IRQ1 IRQ1 Reserved Reserved
R249 R248 R247 R246 R245 R244 R243 R242 R241 R240
Not Implemented
Figure 14. Program Memory Map
R128 R127 R4 R3 R2 R1 R0 General-Purpose Registers Port 3 Port 2 Reserved Port 0 P0 P3 P2
Figure 15. Register File
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Zilog Stack Pointer. The Z86319 features an 8-bit Stack Pointer (R255) used for the internal stack that resides within the general-purpose registers. Counter/Timer. There are two 8-bit programmable counter/timers (T0 and T1), each driven by its own 6-bit programmable prescaler. The T1 prescaler can be driven by internal or external clock sources, however, the T0 can be driven by the internal clock source only (Figure 16). The 6-bit prescalers can divide the input frequency of the clock source by any integer number from 1 to 64. Each prescaler drives its counter, which decrements the value (1 to 256) that has been loaded into the counter. When both counter and prescaler reach the end of count, a timer interrupt request IRQ4 (T0) or IRQ5 (T1) is generated.
Z86319 PS/2 Mouse Controller The counter can be programmed to start, stop, continue, or restart from the initial value. The counters can also be programmed to stop upon reaching zero (single pass mode) or to automatically reload the initial value and continue counting (modulo-n continuous mode). The counters, but not the prescalers, are read at any time without disturbing their value or count mode. The clock source for T1 is user-definable and can be either the internal microprocessor clock divided by four, or an external signal input via Port 3. The Timer Mode register configures the external timer input (P31) as an external clock, a trigger input that is retriggerable or not retriggerable, or as a gate input for the internal clock.
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Internal Data Bus Write PRE0 Initial Value Register OSC 6-Bit Down Counter 8-Bit Down Counter Write T0 Initial Value Register Read T0 Current Value Register
/4 Internal Clock External Clock Clock Logic /4
IRQ4
6-Bit Down Counter
8-Bit Down Counter
IRQ5
TIN P31
Internal Clock Gated Clock Triggered Clock
PRE1 Initial Value Register Write Write
T1 Initial Value Register Read
T1 Current Value Register
Internal Data Bus
Figure 16. Counter/Timers Block Diagram
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FUNCTIONAL DESCRIPTION (Continued)
Interrupts. The Z86319 features four interrupts from four different sources. These interrupts are maskable and prioritized (Figure 17). The four sources are divided as follows: the falling edge of P31, P33, and the two counter/timers. The Interrupt Mask Register globally or individually enables or disables the four interrupt requests (Table 5). When more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority register. All Z86319 interrupts are vectored through locations in program memory. When an interrupt machine cycle is activated, an interrupt request is granted, thereby disabling all subsequent interrupts, saving the Program Counter and Status Flags, and branching to the program memory vector location reserved for that interrupt. This memory location and the next byte contain the 16-bit starting address of the Interrupt Service Routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked and the Interrupt Request Register is polled to determine which of the interrupt requests requires service. Table 5. Interrupt Types, Sources, and Vectors Source P33 P31 T0 T1 Name IRQ1 IRQ2 IRQ4 IRQ5 Vector 2,3 4,5 8,9 10,11 Location Comments External External Internal Internal Falling Edge Falling Edge
IRQ1 - IRQ5
IRQ
IMR 6 IPR
Global Interrupt Enable Interrupt Request
Priority Logic
Vector Select
Figure 17. Interrupt Block Diagram
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Zilog RC Oscillator. The Z86319 features an on-chip RC precision oscillator that requires a 1% precision resistor externally connected between VDD and pin 6 (Figure 18). The tolerance of the RC oscillator is less than 10% over the voltage range of 4.5V to 5.5V and over a temperature range of 0-40C. Pin 7 is the Analog Ground for the oscillator. Increased parasitic board capacitance will slow down the RC oscillator and deteriorate the RC frequency tolerance. The minimum and maximum parasitic board capacitances are 0.5 pF and 2 pF, respectively.
Z86319 PS/2 Mouse Controller In HALT Mode, the value of each output line prior to the HALT instruction is retained. Watch-Dog Timer (WDT). The Watch-Dog Timer is enabled upon power-up of the MCU and is clocked by its own internal RC oscillator. The WDT instruction does not affect the Zero (Z), Sign (S), and Overflow (V) flags. Opcode WDT (5FH). Execution of WDT clears the WDT counter. The time interval between any 2 consecutive WDT instructions has to be smaller than TWDT min. Low Voltage Protection (VLV). The device will function normally between 5.5V and 4.5V under all specified conditions. Below 4.5V, the device is still internally functional until the Low Voltage trip point (VLV) is reached, however, it is not guaranteed to meet all AC and DC Characteristics. When the supply voltage drops below VLV, an automatic hardware reset occurs as VDD returns above VLV. Essentially, this action helps in reinitializing the Z86319. The actual VLV is a function of temperature, operating frequency and process parameters. The typical VLV is a function of the ambient temperature for a frequency of 4 MHz. The device is functional down to VLV voltage. The min. operational VDD is determined by the value of the VLV voltage at ambient temperatures. The VLV voltage increases as the temperature decreases (Figure 19).
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VDD 1% 6 7 RCIN AGND
Precision RC Oscillator
Figure 18. Oscillator Configuration HALT Mode. This instruction turns off the internal CPU clock but not the precision RC oscillator. The counter/timers, their interrupts, and external interrupts IRQ1 and IRQ2 remain active. The device can be recovered by interrupts, either externally or internally generated. An interrupt must be enabled prior to the HALT Mode, and executed to exit the HALT Mode. After the interrupt service routine, the program continues from the instruction after the HALT. In order to enter HALT Mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. To flush the pipeline, the user must execute a NOP (Opcode=FFH) immediately before the HALT instruction. i.e.: FF 7F NOP HALT ; clear the pipeline ; enter the HALT Mode
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FUNCTIONAL DESCRIPTION (Continued)
2.85 2.80 2.75 2.70 2.65 Volts 2.60 VLV (Typical) 2.55 2.50 2.45 2.40 2.35 -5
0
5
10
15
20
25
30 35 40 Temperature (C)
Figure 19. Typical Z86319 VLV vs Temperature
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Z8 CONTROL REGISTERS
R241 TMR D7 D6 D5 D4 D3 D2 D1 D0
R244 T0 D7 D6 D5 D4 D3 D2 D1 D0
1
T0 Initial Value (When Written) (Range: 1-256 Decimal 01-00 HEX) T0 Current Value (When READ)
0 No Function 1 Load T0 0 Disable T0 Count 1 Enable T0 Count 0 No Function 1 Load T1 0 Disable T1 Count 1 Enable T1 Count TIN Modes 00 External Clock Input 01 Gate Input 10 Trigger Input (Non-retriggerable) 11 Trigger Input (Retriggerable) Reserved (Must be 0)
Figure 23. Counter/Timer 0 Register (F4H: Read/Write)
R245 PRE0 D7 D6 D5 D4 D3 D2 D1 D0
Count Mode 0 T0 Single Pass 1 T0 Modulo N Reserved (Must be 0) Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX)
Figure 20. Timer Mode Register (F1H: Read/Write)
R242 T1 D7 D6 D5 D4 D3 D2 D1 D0
Figure 24. Prescaler 0 Register (F5H: Write Only)
T1 Initial Value (When Written) (Range 1-256 Decimal 01-00 HEX) T1 Current Value (When READ)
R246 P2M D7 D6 D5 D4 D3 D2 D1 D0
Figure 21. Counter Timer 1 Register (F2H: Read/Write)
P27- P20 I/O Definition 0 Defines Bit as OUTPUT 1 Defines Bit as INPUT
R243 PRE1 D7 D6 D5 D4 D3 D2 D1 D0
Figure 25. Port 2 Mode Register (F6H: Write Only)
R247 P3M
Count Mode 0 T1 Single Pass 1 T1 Modulo Clock Source 1 T1 Internal 0 T1 External Timing Input (TIN) Mode Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX)
D7 D6 D5 D4 D3 D2
D1
D0
0 1
Port 2 Open-Drain Port 2 Push-Pull
Reserved (Must be 0)
Figure 26. Port 3 Mode Register (F7H: Write Only)
Figure 22. Prescaler 1 Register (F3H: Write Only)
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Z8 CONTROL REGISTERS (Continued)
R248 P01M D7 D6 D5 D4 D3 D2 D1 D0
R251 IMR D7 D6 D5 D4 D3 D2 D1 D0
P00-P03 Mode 0 Output 1 Input Reserved (Must be 0) Don't care Reserved (Must be 0)
1 Enables IRQ (DX = IRQX) Reserved (Must be 0) 1 Enable Interrupts
Figure 27. Port 0 and 1 Mode Register (F8H: Write Only)
Figure 30. Interrupt Mask Register (FBH: Read/Write)
R252 Flags
R249 IPR D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
User Flag F1
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Reserved IRQ1>4>5>2 Reserved IRQ4>1>5>2 IRQ5>2>1>4 IRQ5>1>4>2 IRQ5>2>4>1 IRQ5>4>1>2 IRQ2>1>4>5 IRQ1>4>2>5 IRQ2>4>1>5 IRQ4>1>2>5 IRQ2>5>1>4 Reserved IRQ2>5>4>1 Reserved
User Flag F2 Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag
Reserved (Must be 0.)
Figure 28. Interrupt Priority Register (F9H: Write Only)
R253 RP
R250 IRQ D7 D6 D5 D4 D3 D2 D1 D0 Reserved (Must be 0) IRQ1 = P33 Input IRQ2 = P31 Input Reserved (Must be 0) IRQ4 = T0 IRQ5 = T1 Reserved (Must be 0)
Figure 31. Flag Register (FCH: Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Don't Care Register Pointer
Figure 32. Register Pointer (FDH: Read/Write)
R255 SPL D7 D6 D5 D4 D3 D2 D1 D0
Figure 29. Interrupt Request Register (FAH: Read/Write)
Stack Pointer Lower Byte (SP0-SP7)
Figure 33. Stack Pointer (FFH: Read/Write)
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Z8 PORT REGISTERS
R0 Port 0 D7 D6 D5 D4 D3 D2 D1 D0 R3 Port 3 D7 D6 D5 D4 D3 D2 D1 D0 P00 P01 P02 Reads as "11111" Writing has NO EFFECT
1
Reads 1 P31 Reads 0 P33 Reads 1111
Figure 34. Port 0 Register (Read/Write)
R0 Port 2 D7 D6 D5 D4 D3 D2 D1 D0
P27 P26 P25 P24 P23 P22 P21 P20
Figure 36. Port 3 Register (Read Only)
Figure 35. Port 2 Register (Read/Write)
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PACKAGING INFORMATION
Figure 37. 18-Pin DIP Package Diagram
Figure 38. 18-Pin SOIC Package Diagram
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ORDERING INFORMATION Z86319
Z8631904PSC Z8631904SSC
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For fast results, contact your local Zilog sales offices for assistance in ordering the part required.
CODES
Package P = DIP S = SOIC Temperature S = 0C to +40C Example: Z 86319 0 4 P S C Speed 04 = 4 MHz Environmental C = Plastic Standard
is a Z86319, 4 MHz, DIP, 0 to +40C, Plastic Standard Flow Environmental Flow Temperature Package Speed Product Number Zilog Prefix
(c) 1998 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. ZILOG, INC. MAKES NO WARRANTY, EXPRESS, STATUTORY, IMPLIED OR BY DESCRIPTION, REGARDING THE INFORMATION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE.
Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com
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